Shielded gate trench metal-oxide-semiconductor field-effect transistor MOSFET devices are advantageous in that the shield electrode can be used to reduce the gate-drain capacitance (Cgd) and/or improve the breakdown voltage of the gate trench MOSFET device. In known shielded gate trench MOSFETs, a trench can include a shield electrode disposed below a gate electrode. The shield electrode can be insulated from adjacent silicon regions by a shield oxide (e.g., shield dielectric) which is generally thicker than a gate oxide (e.g., gate dielectric) around the gate electrode. The gate electrode and the shield electrode can be insulated from one another by a dielectric layer referred to as an inter-poly dielectric (IPD) layer. The IPD layer is generally of sufficient quality and thickness to support the required voltage between the gate electrode and the shield electrode.
Known shielded gate trench MOSFET devices can suffer from a number of drawbacks. First, the gate electrode can have sharp bottom corners which, together with the flat top surface of the shield electrode, can lead to relatively high electric fields in these regions. Second, known methods for forming the IPD layer can introduce an oxide layer on the mesas between trenches. This oxide layer may be removed at some point after the gate electrode has been formed; however, when removing this oxide, etching of the gate oxide down the trench walls can occur, which can result in gate shorts and/or gate leakage. Other known techniques tie formation of the IPD layer to formation of the gate dielectric, and thus the IPD layer thickness may be limited to a set multiple of the gate dielectric thickness. This may not allow for independent optimization of the gate dielectric and/or the IPD layer. Thus, there is a need for an apparatus and method related to formation of a shielded gate trench MOSFET device to address the shortfalls of present technology and to provide other new and innovative features.